NationalTechnical Universityof Athens Department of Electrical and Computer Engineering Microelectronic Circuit Design Group

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Yannis Papananos: Complete list of publications

Ph.D. dissertation, 1988.

Books
• Design of Analog Filters, Ch. Halkias, Yannis Papananos, Symmetria Publications, 1987 (in Greek).
• Microelectronic Circuits for Telecommunication Applications, Yannis Papananos, ICCS/NTUA - Papasotiriou Publications, 1998 (in Greek).
• Radio Frequency Microelectronic Circuits for Telecommunication Applications, Yannis Papananos, Kluwer Academic Press, Boston 1999.
• Analog Microelectronic Circuits, Yannis Papananos, under preparation (in Greek).


Book Translations
• Microelectronic Circuits Sedra - Smith, Vol. A, Papasotiriou Publications, 1993 (Greek edition).
• Microelectronic Circuits Sedra - Smith, Vol. B, Papasotiriou Publications, 1994 (Greek edition).


Book Chapters
• CMOS circuits for emerging technologies, Kris Iniewski ed. (to be published)


Lecture notes
• Notes of Laboratory Electronics (3 editions).
• Exercises of Laboratory Electronics (3 editions).
• Introduction in VLSI Systems.
• Modeling of active and passive silicon integrated devices for HF applications.


CD - ROMs
• CD - ROM of Laboratory Electronics, 1st edition, 1997.
• CD - ROM of Laboratory Electronics, 2nd edition, 1999.


Software Products
• XCAP - Graphic Environment for use in SWITCAP 2 Program, 1994.
  A CAD tool product in cooperation with Columbia University, USA. This program is available in the international market by the CIE organization of Columbia University. Over than 50 copies are already sold in companies and Universities in Europe, USA, ASIA and Oceania. Some of the companies are: Motorola, Siemens, Sharp, Texas Instruments, etc.
• XCAP - SISP - Silicon Inductor Simulation Program, 1998.
  A research product of the Microelectronic Circuits Design Group and it is sold through ICCS/NTUA in the international market. It has already been advertised in the international edition of Microwave Journal, Nov./Dec. 1998. It has already been bought by large companies and Universities all over the world. Some are: Thomson CSF, ST Microelectronics, AMS, ATMEL, etc. Also, some of the major electronics and telecommunication companies in the world have expressed interest in buying the product like Texas Instruments (USA), Lucent Technologies (USA), IBM (USA), ERICSSON (Sweden), Samsung (Korea), etc.
• XCAP - MOSBENCH - Automatic Characterization of MOS Transistor Models for Circuit Simulators, 2005.
  A research product of the Microelectronic Circuit Design Group, integrated in the Cadence environment. The tool is used to automatically execute benchmark tests for the reliability of any MOS transistor model in any given technology implemented in the Cadence design environment.


Publications in International Journals
1. Feasibility of Analog Computation for Image Processing Applications, Y. Papananos, IEE Proceedings, Vol. 136, Pt. G, No. 1, Feb. 1989, pp. 9-13.
2. A New Wiring Architecture for Parallel Processing Applications, Y. Papananos, Integration, The VLSI Journal, 10, (1990), pp. 71-88.
3. Analysis and VLSI Architecture of a Nonlinear Edge-Preserving Noise-Smoothing Image Filter, Y. Papananos and D. Anastassiou, IEE Proceedings, Vol. 138, Pt. G, No. 4, Aug. 1991, pp. 433-440.
4. Continuous-Time Filters Using Buffers with Gain Lower Than Unity, Y. Tsividis and Y. Papananos, Electronics Letters, Vol. 30, No. 8, 14th April 1994, pp. 629-630.
5. A Si 1.8 GHz RLC Filter with Tunable Center Frequency and Quality Factor, S. Pipilos, Y. Tsividis, J. Fenk, and Y. Papananos, IEEE Journal of Solid-State Circuits, vol. 31, Oct. 1996, pp.1517-1525.
6. Six-Terminal MOSFET's: Modelling and Applications in Highly-Linear Electronically Tunable Resistors, K. Vavelidis, Y.Tsividis, F. Op't Eynde and Y. Papananos, IEEE Journal of Solid-State Circuits, vol. 32, Jan. 1997, pp.4-12.
7. Design Considerations and Implementation of Very Low Frequency Continuous-Time CMOS Monolithic Filters, Y. Papananos, T. Georgantas and Y. Tsividis, IEE Proceedings Pt. G, Vol. 144, No. 2, Apr. 1997, pp. 68-74.
8. Systematic Analysis and Modeling of Integrated Inductors and Transformers in RF IC Design, Y. Koutsoyannopoulos and Y. Papananos, IEEE Transactions on Circuits and Systems, Vol. 47, Issue 8, pp. 699-713, Aug. 2000.
9. Passive on-chip components for fully integrated silicon RF VCOs, A. Kyranas and Y. Papananos, Active and Passive Elec. Comp., 2002, Vol. 25, pp. 83-95.
10. Convergence Free Predistortion Technique for Adaptive Linearisation of RF Power Amplifiers, N. Naskas, Y. Papananos, Kluwer, Analog Integrated Circuits and Signal Processing J., 41, pp.109-118, 2004.
11. Neural Network Based Adaptive Baseband Predistortion Method for RF Power Amplifiers, N. Naskas, Y. Papananos , IEEE, Trans. on Circuits and Systems II, vol. 51, no. 11, pp. 619-623, Nov. 2004.
12. A Novel Non-Iterative Adaptive Baseband Predistorter for PA Linearisation, N. Naskas, Y. Papananos, IEE Proceedings.
13. A High Counting Rate Readout System for X-ray Applications, E. Zervakis, Y. Papananos, D. Loukas, N. Haralambidis, A. Pavlidis, IEEE, Trans. Nuclear Science, Vol. 51, No. 4, pp. 1840-1847, August 2004.
14. A Transmitter IC for TETRA Systems Based on a Cartesian Feedback Loop Linearization Technique, S. Pipilos, Y. Papananos, N. Naskas, E. Zervakis, B. Carter, G. Dann, J. Jongsma, T. Ghsier, IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 707-718.
15. RF operation of MOSFETs under integrated inductors, N. Nastos and Y. Papananos, IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 5, pp. 2106 - 2117
16. A Low-Power Wideband Reconfigurable Integrated Active-RC Filter with 73 dB Dynamic Range, IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 1997 - 2008.
17. A 1-V, 5.5-GHz, CMOS LNA with Multiple Magnetic Feedback, Vitzilaios G. ; Papananos Y. ; Theodoratos G. ; Vasilopoulos A., IEEE, Trans. on Circuits and Systems II, Sep. 2006
18. Magnetic-Feedback Based Predistortion Method for Low-Noise Amplifier Linearization, G. Vitzilaios, Y. Papananos, G. Theodoratos, K. Vryssas, IEEE, Trans. on Circuits and Systems II, Dec. 2006
19. A Low Voltage, 5 GHz Down Conversion Mixer Employing a 2nd Harmonic Injection Linearization Technique, G. Theodoratos, Y. Papananos, G. Vitzilaios, IEEE Trans. on Circuits and Systems II, Nov. 2007
20. A Magnetic Feedback Method for CMOS LNA Reverse Isolation Enhancement, G. Vitzilaios, Y. Papananos, to appear in IEEE TCAS-II.
21. A 1-V, 5 GHz CMOS Receiver Front-End for Broadband Wireless Applications, G. Theodoratos, G. Vitzilaios, A. Vassilopoulos, Y. Papananos, to appear in IEEE MTT.
22. Self-Bias Re-use for Improving the Power Capability of Wireless Power Amplifiers, K. Vryssas, Y. Papananos and A. Samelis, IEEE TCAS-II, under review.


Publications in International Conferences
1. Adequacy of Voltage Control for Compensating Process and Temperature Variations in MOS Active RC Filters, M. Banu, Y. Tsividis and I. Papananos, Proc. 1984 IEEE ISCAS, Montreal, Canada, pp. 936-939.
2. A VLSI Architecture for a Nonlinear Edge-Preserving Noise-Smoothing Image Filter, Y. Papananos and D. Anastassiou, SPIE Vol. 845, Visual Communications and Image Processing II (1987), Cambridge Massachussetts, pp. 321-328.
3. Analysis and Design of a Nonlinear Edge-Preserving Noise-Smoothing Image Filter, Y. Papananos and J. Moondanos, EUSIPCO 1988, Signal Processing IV, Theories and Applications, pp. 1589-1592.
4. A Comparative Study of Five Integrator Structures for Monolithic Continuous-Time Filters - A Tutorial, T. Georgantas, Y. Papananos and Y. Tsividis, Proc. 1993 IEEE ISCAS, Chicago, USA, vol. 2, pp. 1259-1262.
5. Design Considerations and Implementation of Very Low Frequency Continuous-Time CMOS Monolithic Filters, Y. Papananos, T. Georgantas and Y. Tsividis, Proc. IEEE ICECS 96, Rodos, Greece, pp. 223-226.
6. ALCD - Analog Libraries on CMOS Digital Process,C. Dupuy, J.E. Franca, C. Azeredo Leme, F. Maloberti, R. Rivoir, G. Torelli, Y. Papananos, Proc. IEEE ICECS 96, Rodos, Greece, pp. 618-622.
7. Design and Implementation of a CMOS Operational Amplifier Architecture with Dual Common-Mode Feedback Loop,Y. Papananos and Y. Tsividis, Proc. IEEE ICECS 96, Rodos, Greece, pp. 904-907.
8. A Generic CAD Model for Arbitrarily Shaped and Multi-Layer Integrated Inductors on Silicon Substrates, Y. Koutsoyannopoulos, Y. Papananos, C. Alemanni, S. Bantas Proc. ESSCIRC '97, pp. 320-323, Southampton UK, Sep. 1997.
9. A CAD tool for Simulating the Performance of Polygonal and Multi-Layer Integrated Inductors on Silicon Substrates, Y. Koutsoyannopoulos, Y. Papananos, Proc. IEEE 5th International Conference on VLSI and CAD (ICVC '97), Seoul-Korea, 1997, pp. 244-246.
10. A uW-power Continuous-time Current-mode Filter in a Digital CMOS Process, S. Bantas, and Y. Papananos, Proc. IEEE 5th International Conference on VLSI and CAD (ICVC '97), Seoul-Korea, 1997, pp. 346-348.
11. Efficient Utilization of On-chip Inductors in Silicon RF IC Design Using a Novel CAD Tool; The LNA Paradigm, Y. Papananos, Y. Koutsoyannopoulos, Proc. 1998 IEEE ISCAS, Monterey, USA, pp. 118-121.
12. Device Modeling and Applications in Silicon RF IC Design, Y. Papananos, Y. Koutsoyannopoulos, S. Bantas, 1998 International Conference on Telecommunications, Proc. ICT '98, pp. 125-129, vol. IV, Jun. 1998, Chalkidiki, Greece.
13. Design Issues Towards the Integration of Passive Components in Silicon RF VCOs, A. Kyranas and Y. Papananos, IEEE ICECS 98, Lisboa, Portugal, pp. 311-314.
14. Novel Si Integrated Inductor and Transformer Structures for RF IC Design, Y. Koutsoyannopoulos, Y. Papananos, S. Bantas, C. Alemanni, 1999 IEEE ISCAS, Orlando, USA.
15. CMOS Tunable Bandpass Filters Utilizing Coupled on-chip Inductors, S. Bantas and Y. Papananos, 1999 IEEE ISCAS, Orlando, USA.
16. A Comparison Between Current and Voltage Mode Filters for Wireless Communication Systems, T. Georgantas, S. Bouras, D. Dervenis, Y. Papananos, 1999 IEEE ICECS, Pafos, Cyprus.
17. Current Mode Baseband Interface for Communication Applications, S. Bouras, T. Georgantas, Y. Papananos, D. Dervenis, 1999 IEEE ICECS, Pafos, Cyprus.
18. A 5 GHz Fully Integrated VCO in a SiGe Bipolar Technology, A. Kyranas and Y. Papananos, 2000 IEEE ISCAS, Geneva, Switzerland.
19. Switched-Current ΣΔ Modulator for Baseband Channel Applications, T. Georgantas, S. Bouras, Y. Papananos, D. Dervenis, 2000 IEEE ISCAS, Geneva, Switzerland.
20. Performance Limits of Planar and Multilayer Integrated Inductors, Y. Koutsoyannopoulos, Y. Papananos, S. Bantas, C. Alemanni, 2000 IEEE ISCAS, Geneva, Switzerland.
21. Design issues of fully integrated RF VCOs, A. Kyranas and Y. Papananos, MMN2000, Demokritos, Athens.
22. Power Amplifier Linearization Techniques: An Overview, N. Naskas and Y. Papananos, MMN2000, Demokritos, Athens. Also in Microelectronics, Microsystems and Nanotechnology, World Scientific Press.
23. MOSFET Model Benchmarking Using a Novel CAD Tool, N. Nastos and Y. Papananos, MMN2000, Demokritos, Athens. Also in Microelectronics, Microsystems and Nanotechnology, World Scientific Press.
24. A CAD Ξ€ool for Benchmarking MOSFET Models, N. Nastos and Y. Papananos, IEEE ISCAS 2001.
25. Adaptive Baseband Predistorter for Radio Frequency Power Amplifiers Based on a Multilayer Perceptron, N. Naskas and Y. Papananos, IEEE ICECS 2002.
26. Baseband Predistorter for Radio Frequency Power Amplifiers Based on a Non-Iterative, Fast Adaptation Method, N. Naskas and Y. Papananos, IEEE ICECS 2002. Best Student Paper Award.
27. High Frequency Operation of a MOSFET Under an Integrated Inductor's Magnetic Field, N. Nastos and Y. Papananos, IEEE ICECS 2002.
28. Analysis of Transconductance at All Levels of Inversion in Deep Submicron CMOS, M. Bucher, D. Kazazis, F. Krummenacher, D. Binkley, D. Foty, Y. Papananos, IEEE ICECS 2002.
29. An adaptive power amplifier lineariser based on a multilayer perceptron, N. Naskas, Y. Papananos, IEEE VTC 2003.
30. A new non-iterative, adaptive baseband predistortion method for high power RF amplifiers, N. Naskas, Y. Papananos, IEEE ISCAS 2003.
31. Integrated inductors over MOSFETs experimental results of a three dimensional integrated structure, N. Nastos, Y. Papananos, IEEE ISCAS 2003.
32. Development Of A High Count Rate Readout System Based On A Linear Transimpedance Amplifier For X-ray Imaging, E. Zervakis, Y. Papananos, D. Loukas, N. Haralambidis, A. Pavlidis, 2003 IEEE NSS MIC.
33. Integrated inductors over MOSFETs: Study of the EM effects, Y. Papananos, N. Nastos, IEEE Int. Conf. Microelectronics 2004, invited paper.
34. Analysis of Harmonic Distortion in Deep Submicron CMOS, M. Bucher, A. Bazigos, N. Nastos, Y. Papananos, F. Krummenacher, S. Yoshitomi, 2004 IEEE ICECS 2004.
35. A low-voltage, highly linear, integrated, active-RC filter, Vasilopoulos, A.; Vitzilaios, G.; Theodoratos, G.; Papananos, Y.;Research in Microelectronics and Electronics, 2005 PhDVolume 1, 25-28 July 2005 Page(s): 39 - 42 vol.1
36. A Low-Voltage CMOS LNA with Multiple Magnetic Feedback for WLAN Applications, G. Vitzilaios, G. Theodoratos, A. Vasilopoulos, Y. Papananos, IEEE ISCAS 2006.
37. Calculating Distortion in Active CMOS Mixers Using Voltera Series, G. Vitzilaios, G. Theodoratos, A. Vasilopoulos, Y. Papananos, IEEE ISCAS 2006.
38. A User-Friendly Benchmark Tool for MOS Models, 2006 MIXDES Conference
39. Scaling Issues In An 0.15 um CMOS Technology With EKV3.0, Kitonaki E., Bazigos A., Bucher M., Puchner H., Bhardwaj S., Papananos Y.Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
40. Design and Implementation of a 1-V Low Flicker Noise Direct Conversion Mixer at 5.5 GHz using a 90nm CMOS RF Technology, P. Simitsakis, A. Bazigos, Y. Papananos, to appear in IEEE ICECS 2007 Conference.

Patents
• An Integrated High-Frequency Balanced-to-Unbalanced Transformer, US patent 7,253,712
• Low Noise Amplifier, a pending US patent application number 11/803,509
• Highly Linear Low-Noise Amplifier, a pending US patent application number 11/801,945
• Programmable Filters and Methods Thereof, a pending US patent application number 11/590,599
• Integrated High Frequency BALUN and Inductors, a pending US patent application that is a continuation-in-part of , US patent 7,253,712


e-mail: papan@elab.ntua.gr

 

 

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